Advances in semiconductor design and processing have provided very complex semiconductor chips which are now several hundred mils on a side and dissipate watts of power. The aforesaid size and power requirements have also increased the complexity and cost of providing interconnections and packaging for semiconductor chips. As chip yields improve and the cost per chip declines, the cost of interconnecting and packaging the chip becomes a significant part of the total cost of providing circuits such as memories, central processors, amplifiers, or custom integrated circuits.
To reduce cost and increase reliability, some interconnection designs mount one or more semiconductor chips on insulator substrates such as a ceramic or a printed wiring board. Printed wiring boards may be either flexible or rigid. Many of these substrate designs require multilayer conductor planes due to the size and complexity of the newer semiconductor chips. Multilayer printed wiring boards are more expensive than just top and/or lower printed wiring boards and therefore add to the overall cost of each system they are a part of.
Attempts have been made to use the area under a chip to route conductors. U. S. Pat. No. 4,595,945 (R. N. Grover) employs a structure which has a support paddle of a lead frame which is split electrically to provide conductor members that cross under the chip after the chip is bonded to the paddle. The chip is electrically isolated from the crossunder members by a separate Kapton film which is inserted between the lead frame and the chip. Wire bonds are made from the upper surface of the chip down to the lead frame to make the connections which are prevented by the Kapton film. This not only increases the number of wire bonds but the Kapton film also acts as a thermal barrier in the removal of heat from the chip. Assembly of the Grover structure is also complicated by the need to insert, accurately locate, and bond a Kapton film between the chip and split paddle lead frame. Another complication is in the wire bonding operation because the upper plane of the chip bonding sites is above the plane of the lead frame by the thickness of the Kapton film, the adhesive, and the chip. This requires longer loops on the wire bonds which increases the space needed between wire bond sites to prevent short circuits during vibration.
U. S. Pat. No. 3,374,537 (W. L. Doelp, Jr.) employs a transparent glass substrate having an upper surface on which is defined a conductor pattern to interconnect the contact area and interconnection film of one monolithic flip chip to the contact area and interconnection film of another. The transparent substrate is preferred for face down chip bonding, but this limits the heat dissipation capability due to the lower thermal conductivity of glass as compared to ceramic substrates. In addition, with face-down chip attachment, the back surface of the chip is not attached to a heat sink. Thus, all the heat generated by the chip must be transferred to the substrate by conduction through the small areas of the solder bumps between the chip and substrate.
It is desirable to provide an interconnect apparatus which can be used to interconnect a semiconductor chip to other chips and/or components and can provide an electrical crossover in the area above a semiconductor chip while having the substrate of the chip bonded to a heat sink.